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fn8878 rev.1.00 page 1 of 41 aug 30, 2017 fn8878 rev.1.00 aug 30, 2017 isl8215m 15a 42v single-channel dc/dc step-down power module datasheet the isl8215m power module is a single-channel, synchronous step-down, non-i solated complete power supply, capable of delivering up to 15a of continuous current. operating from a single 7v to 42v wide input power rail and integrating the controller, power inductor, and mosfets, the isl8215m req uires only a few external components to operate and is optimized for space constrained applications. based on a valley current mode pwm control scheme, the isl8215m provides fast trans ient response and excellent loop stability. it offers an adjustable output voltage range of 0.6v to 12v with better than 1.5% accuracy over line, load, and temperature. a 40ns typi cal minimum on time and an adjustable operating frequency allow it to support low duty cycle, single-step down conv ersions to point-of-load voltages and its operating frequency can also be synchronized with an external c lock signal. the isl8215m implements a selectable puls e skipping mode (psm) with diode emulation mode (dem) to improve light-load efficiency for battery related applications. a programmable soft-start reduces the inrush current from the input supply while a dedicated enable pin and power-good flag allow for easy system power rails seque ncing with voltage tracking capability. excellent efficiency and low thermal resistance permit full power operation without heatsinks. input undervoltage lockout ( uvlo), over-temperature, programmable overcurrent, output overvoltage, and output prebias start-up protections e nsure safe operations under abnormal operating conditions. the isl8215m is available in a compact rohs compliant thermally-enhanced 19mmx 13mmx5.3mm hda package. features ? 15a single-channel complete power supply ? integrates controller, mosfets, and inductor ? 7v to 42v wide input voltage range ? adjustable output voltage ? 0.6v to 12v wide output voltage range ? 40ns on-time low duty cycle conversion capable ? 1.5% accuracy over line, load, and temperature ? up to 96.5% efficiency ? 300khz to 2mhz adjust able pwm operations ? external synchronization up to 1mhz ? selectable light-load psm/dem efficiency mode ? enable pin and power-good flag ? programmable soft-start or voltage tracking ? complete protection ? uvlo, programmable overcurrent, overvoltage, and over-temperature ? prebias output start-up ? 19mmx13mmx5.3mm hda package applications ? industrial and medical equipment ? aftermarket automotive ? telecom and dat acom equipment related literature ? for a full list of related documents, visit our website ? isl8215m product page figure 1. typical application circuit figure 2. v in = 24v isl8215m 7v to 42v input c in c out 5v 15a output 20 enable power good 10f 2 1f 4.02 270pf ?? ?? ?? ph vin1 vin vout en pgood vcc mod/sync rt ss/trk sgnd vout1 fb ocs pgnd rs 205k ?? 5.9k ?? ???? ? ? ? ???
isl8215m fn8878 rev.1.00 page 2 of 41 aug 30, 2017 table of contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2. specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 thermal information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3. typical performance curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 efficiency performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 load transient response performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 start-up waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 power-good indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 self-enable operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4 prebiased power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 pwm/ccm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6 psm/dem light-load effici ency mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7 internal 5v linear regu lator (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.8 gate control logic optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 output voltage programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 external frequency synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 5.4 soft-start operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 tracking operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.6 input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.7 input capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.8 output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. protection circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2 overcurrent protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4 over-temperature protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
isl8215m fn8878 rev.1.00 page 3 of 41 aug 30, 2017 7. layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8. thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9. package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.1 pcb layout pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.2 thermal vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.3 stencil pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.4 reflow parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10. revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11. package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12. about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
isl8215m 1. overview fn8878 rev.1.00 page 4 of 41 aug 30, 2017 1. overview 1.1 typical application circuits figure 3. v out = 1.2v, f sw = 300khz, light-load mode, t ss = 15ms figure 4. v out = 3.3v, f sw = 300khz, light-load mode, t ss = 15ms isl8215m 7v to 28v input cin_ceramic 1.2v 15a output r1 20 r4 100k enable power good 47nf r3 2 1f 43.2k dnp r5 4.02 c2 270pf cin_bulk 4x10f 100f css 10f c_vcc + cout_bulk 470f + cout_ceramic 4x100f cout1 r2 rocset ph vout rs ug1 ug2 comp vout1 fb ocs pgnd sgnd ss/trk rt mod/sync vcc pgood en vin vin1 isl8215m 7v to 42v input cin_ceramic 3.3v 15a output r1 20 r4 100k enable power good 47nf r3 2 1f 9.53k dnp c2 270 pf cin_bulk 4x10f 100f css 10f c_vcc + cout_bulk 470f + cout_ceramic 4x100f cout1 r2 rocset ph vout rs ug1 ug2 comp vout1 fb ocs pgnd sgnd ss/trk rt mod/sync vcc pgood en vin vin1 r5 4.02
isl8215m 1. overview fn8878 rev.1.00 page 5 of 41 aug 30, 2017 figure 5. v out = 5v, f sw = 300khz, light-load mode, t ss = 15ms figure 6. v out = 12v, f sw = 600khz, pwm only, t ss = 15ms isl8215m 7v to 42v input cin_ceramic 5v 15a output r1 20 r4 100k enable power good 47nf r3 2 1f 5.9k 205k r5 4.02 c2 270 pf cin_bulk 4x10f 100f css 10f c_vcc + cout_bulk 330f + cout_ceramic 4x100f cout1 r2 rocset ph vout rs ug1 ug2 comp vout1 fb ocs pgnd sgnd ss/trk rt mod/sync vcc pgood en vin vin1 isl8215m 16v to 42v input cin_ceramic 12v 15a output r1 20 r4 100k enable power good 47nf r3 2 1f 2.26k 118k r5 4.02 c2 270pf cin_bulk 4x10f 100f css 10f c_vcc + cout_bulk 2x150f + cout_ceramic 12x22f cout1 r2 rocset 100pf c7 ph vout rs ug1 ug2 comp vout1 fb ocs pgnd sgnd ss/trk rt mod/sync vcc pgood en vin vin1
isl8215m 1. overview fn8878 rev.1.00 page 6 of 41 aug 30, 2017 1.2 block diagram 1.3 ordering information figure 7. block diagram rt en sgnd mod/sync vcc comp fb ocs pgnd vout1 ph vin internal regulator gm internal reference soft-start and fault logic gate control logic oscillator pgood pwm controller 2.2h ug1 + - + - comp network d1 ss/trk rs 0.1f vin1 vout 43.2k 1% ug2 ?? 49.9 1% ?? 1.5m ?? ? ? ? ? ?? ? ?? ??? ? ISL8215MIRZ isl8215m -40 to +125 19x13 hda y22.19x13 isl8215meval1z evaluation board notes: 1. add -t suffix for 350 unit or -t1 suffix for 100 unit tap e and reel options. refer to tb347 for details on reel specifications. 2. these intersil plastic packaged products are rohs compliant b y eu exemption 7c-i and employ special pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 te rmination finish which is compatible with both snpb and pb- free soldering operations. intersil rohs compliant products are msl classified at pb-free peak reflow temperatures that meet o r exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), see product information page for isl8215m . for information on moisture sensitivity level (msl), see tb363 .
isl8215m 1. overview fn8878 rev.1.00 page 7 of 41 aug 30, 2017 1.4 pin configuration 1.5 pin descriptions isl8215m (22 ld 19x13 hda) to p vi e w 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m pin# 1 pad2 pad5 pad4 pad3 pad1 19mm 13mm 5.3mm pin number pin name function pad1 sgnd signal ground. the small-signal ground is common to all control circuitry and all voltage levels are measured with respect to this pin. sgnd should be tied to a solid low no ise gnd plane. see layout considerations on page 28 and figure 48 on page 29 for details. pad2 vout regulated power supply output. output load should be ap plied between this pin and pgnd. an external resistor on the fb pin sets the output voltage in a range of 0. 6v to 12v. refer to derating curves for maximum load current at various output voltage. pad3 pgnd power ground. this pin is connected to the source of th e lower mosfet inside the module and should be connected to the (-) terminals of the external input capacitors and output capacitors. pad4 vin power input. this pin s hould be connected directly to an input rail in a range of 7v to 42v. input ceramic capacitors should be connected bet ween this pin and pgnd as clo se as possible to the device. pad5 ph phase node connection. this pin is connected to the junct ion of the high-side mosfets source, output filter inductor, and low-side mosfets drain. for a switching frequenc y of 300khz and a 42v input, a 4.02 1206 resistor and a 270pf x7r 100v 0603 capacitor in series from ph to vin (see figures 3 through 6 ) are required. refer to layout considerations on page 28 for details. a1 comp voltage error amplifier output. internal compensation net works are implemented to stabilize the system and achieve optimal transient respons e across the full range of inp ut and output operating conditions. leave this pin floating. a2 ss/trk soft-start/tracking pin . connecting a capacitor from th is pin to signal ground sets the soft-start output voltage ramp rate. for tracking control, an external supply rail applie d to this pin via a resistor divider will be tracked by the output voltage. leave this pin floating to enable a soft-st art time of 1.5ms. refer to tracking operation on page 23 . a3 rt switching frequency selection. connect to sgnd to set the oper ating frequency to 300khz. connect to vcc or float this pin to set the operating frequency to 600khz. connect a resistor from rt to sg nd to program the switching fre quency. refer to the switching frequency selection on page 21 . a4 pgood open-drain, power-good out put. pgood signal is asserted when the output voltage is within 12.5% of the nominal set output voltage and de-asserted when the output volt age is outside of the stated range or the en pin is pulled low.
isl8215m 1. overview fn8878 rev.1.00 page 8 of 41 aug 30, 2017 a5 mod/sync light-load mode selection/synchronization input. connect to vcc to enable light load psm/dem mode with pulse ski pping at light loads. connect to sgnd or leave floati ng to enable constant frequency pwm only mode. connect to external clock to synch ronize the internal switching operations to an external clock; pwm mode only. a6, a8 en enable inputs. connect to logic high level or left floating to enable the devi ce. an internal pull-up resistor allows for self enable operations upon application of vin. connect to logic low level or s gnd: disables the device. these two pins should be connec ted together externally through a pcb trace. b7 vin1 this pin should be tied to the input rail through a 20 0 603 resistor. it provides power to the internal linear drive circuitry and is also used by the feed-forward controller to adjust the amplitude of the pwm sawtooth. c1 fb feedback input. connect a res istor between this pin and sgn d to adjust the output voltage. refer to output voltage programming on page 21 . d1 rs output voltage remote sense feedback. connect to the positi ve output regulation point. to achieve best regulation performance, connect a 2 resistor between the rs pi n and the point of load. an internal 49.9 resistor connected between the rs pin and the vout1 pin can be used for injecting a small signal for loop gain measurements. d6 ug1 high-side mosfet gate dr iver output. connect this pin to u g2, externally through a pcb trace. k4 ug2 pin connected to the gate of high-side mosfet. connect thi s pin to ug1 externally through a pcb trace. e1 vout1 power supply output. connec t a 1f ceramic decoupling ca pacitor between this pin and sgnd. e2 ocs low-side mosfet gate driver output and oc set pin. resisto r between this pin and ground is used to set the overcurrent threshold. inside the module, a 26.1k resistor is c onnected between this pin and sgnd. an external resistor in parallel wi th the internal 26.1k resistor can be used to reduce the overcurrent threshold. refer to overcurrent protection on page 26 for more details. e3 vcc 5v internal linear regulator output. this output supplies bias for the ic, the low-side gate driver and the internal boot circuitry for the high-side gate driver. decouple with a 1 0f ceramic capacitor placed close to the pin to power ground. do not allow the voltage at vcc to exceed vin at any time. c8 nc no connection pin. do not connect these pins. d8 nc pin number pin name function
isl8215m 1. overview fn8878 rev.1.00 page 9 of 41 aug 30, 2017 table 1. isl8215m design g uide matrix (refer to figures 3 through 6 ) case v in (v) v out (v) r2 (k) c in (bulk) (f) c in (ceramic) (f) c out (bulk) (f) c out (ceramic) (f) freq (khz) rt config rocset (k) c 7 (pf) r5 (package) ( note 4 ) 1 12 0.8 130 1x100 4x10 1x470 4x100 300 sgnd dnp open 0402 2 12 0.9 86.6 1x100 4x10 1x470 4x100 300 sgnd dnp open 0402 3 12 1 64.9 1x100 4x10 1x470 4x100 300 sgnd dnp open 0402 4 12 1.2 43.2 1x100 4x10 1x470 4x100 300 sgnd dnp open 0402 5 12 1.8 21.5 1x100 4x10 1x470 4x100 300 sgnd dnp open 0402 6 12 2.5 13.7 1x100 4x10 1x470 4x100 300 sgnd dnp open 0402 7 12 3.3 9.65 1x100 4x10 1x470 4x100 300 sgnd dnp open 0402 8 12 5 5.90 1x100 4x10 1x330 4x100 300 sgnd 205 open 0402 9 24 0.9 86.6 1x100 4x10 1x470 4x100 300 sgnd dnp open 0603 10 24 1 64.9 1x100 4x10 1x470 4x100 300 sgnd dnp open 0603 11 24 1.2 43.2 1x100 4x10 1x470 4x100 300 sgnd dnp open 0603 12 24 1.8 21.5 1x100 4x10 1x470 4x100 300 sgnd dnp open 0603 13 24 2.5 13.7 1x100 4x10 1x470 4x100 300 sgnd dnp open 0603 14 24 3.3 9.65 1x100 4x10 1x470 4x100 300 sgnd dnp open 0603 19 24 5 5.90 1x100 4x10 1x330 4x100 300 sgnd 205 open 0603 20 7 to 42 1.5 28.7 1x100 4x10 1x470 4x100 300 sgnd dnp open 1206 21 7 to 42 1.8 21.5 1x100 4x10 1x470 4x100 300 sgnd dnp open 1206 22 7 to 42 2.5 13.7 1x100 4x10 1x470 4x100 300 sgnd dnp open 1206 23 7 to 42 3.3 9.65 1x100 4x10 1x470 4x100 300 sgnd dnp open 1206 24 7 to 42 5 5.90 1x100 4x10 1x330 4x100 300 sgnd 205 open 1206 27 16 to 42 12 2.26 1x100 4x10 2x150 12x22 600 open 118 100 1210 note: 4. refer to layout considerations on page 28 for more details about package selection size for r5. table 2. recommended input/output capacitor vendor value part number murata, output ceramic 100f, 10v, 1210 grm32er61a107me20l murata, output ceramic 22f, 16v, 1210 grm32er71c226ke18l murata, input ceramic 10f, 50v, 1210 grm32er71h106ka12l panasonic, output bulk 470f, 6.3v 6tpf470mah panasonic, output bulk 330f, 6.3v 6tpf330m9l panasonic, output bulk 150f, 16v 16tqc150myf united chemi-con, input bulk 100f, 50v emza500ada101mha0g murata 270pf, 100v, x7r grm188r72a271ka01d
isl8215m 2. specifications fn8878 rev.1.00 page 10 of 41 aug 30, 2017 2. specifications 2.1 absolute maximum ratings 2.2 thermal information 2.3 recommended operating conditions parameter minimum maximum unit vcc to sgnd -0.3 +5.9 v vin to pgnd -0.3 +45 v vin1 to pgnd -0.3 +45 v en, pgood, ss/trk, fb, comp to sgnd -0.3 v cc + 0.3 v vout to pgnd -0.3 16 v vout1 to pgnd -0.3 16 v rs to pgnd -0.3 16 v ug1 to phase -0.3 v cc + 0.3 v ug2 to phase -20 +20 v ocs to sgnd -0.3 v cc + 0.3 v rt, mod/sync to sgnd -0.3 v cc + 0.3 v esd rating value unit human body model (tested per js-001-2014) 2 kv machine model (tested per jesd22-a115c) 200 v charged device model (tested per js-002-2014) 750 v latch-up (tested per jesd78e; class ii, level a, +125c) 100 ma caution: do not operate at or near the maximum ratings listed f or extended periods of time. ex posure to such conditions may adversely impact produc t reliability and resu lt in failures not covered by warranty. thermal resistance (typical) ? ja (c/w) ? jc (c/w) 22 ld hda package ( notes 5 , 6 )11.7 1.9 notes: 5. ? ja is measured in free air with the module mounted on a 4-layer t hermal test board 4.5x3 inch in s ize with significant coverage of 2.8oz cu on top and bottom and 2oz cu on buried plane layers , with numerous vias. 6. for ? jc , the case temp location is the center of the package undersi de. parameter minimum maximum unit storage temperature range -65 +150 c pb-free reflow profile refer to tb493 parameter minimum maximum unit v in to gnd 7 42 v output voltage, v out 0.612v junction temperature range, t j -40 +125 c
isl8215m 2. specifications fn8878 rev.1.00 page 11 of 41 aug 30, 2017 2.4 electrical specifications unless otherwise noted, typical specifications are measured at v in = 7v to 42v, v out = 1.2v, c_v cc = 10f, t a = +25c. boldface limits apply across the internal junction temperature range, -40c to +125c . parameter symbol test conditions min (note 9) typ max (note 9) unit v in supply input voltage range v in 7 42 v controller input current shutdown current (note 7) i vin1q en = 0 pgood is floating v in1 = 12v 5 10 a operating current (note 8) i vin1op pgood is floating v in1 = 12v 2.5 4 ma v cc supply (note 7) internal ldo output voltage v cc v in = 12v, i l = 0ma 4.85 5.10 5.40 v v in > 7v, i l = 75ma 4.75 5.05 v maximum supply current of internal ldo i vcc_max v vcc = 0v, v in = 12v 120 ma output regulation output continuous current range i out 015 a output voltage range (note 13) v out_range 0.6 12.0 v output voltage set-point accuracy v out_accy total variation with line, load, and temperature (-40c t j +125c) -1.5 1.5 % line regulation ? v out/ v out_set v in from 7v to 42v, i out = 0a to 15a 0.1 % load regulation ? v out/ v out_set from 0a to 15a, v in = 7v to 42v 0.3 % output ripple voltage v out(ac) v in = 24v, v out = 1.2v, i out = 15a, 4x100f ceramic capacitor and 1x470f poscap 13 mv p-p dynamic characteristics voltage change of positive load step v out_dp current slew rate = 2.5a/s, v in = 24v, 4x100f ceramic capacitor and 1x470f poscap v out = 1.2v, i out = 0a to 7.5a 60 mv voltage change of negative load step v out_dn current slew rate = 2.5a/s, v in = 24v, 4x100f ceramic capacitor and 1x470f poscap v out = 1.2v, i out = 7.5a to 0a 60 mv undervoltage lockout undervoltage lockout, rising v uvlothr v in voltage, 0ma on v cc 3.70 3.90 4.20 v undervoltage lockout, falling v uvlothf v in voltage, 0ma on v cc 3.35 3.50 3.85 v en threshold en rise threshold v enss_thr v in = 12v 1.25 1.60 1.95 v en fall threshold v enss_thf v in = 12v 1.05 1.25 1.55 v en hysteresis v enss_hyst v in = 12v 180 350 500 mv soft-start current ss/trk soft-start charge current i ss ss/trk = 0v 2 a default internal minimum soft-starting default internal output ramping time t ss_min ss/trk open 1.5 ms power-good monitors
isl8215m 2. specifications fn8878 rev.1.00 page 12 of 41 aug 30, 2017 pgood upper threshold v pgov 109.0 112.5 115.0 % pgood lower threshold v pguv 85.0 87.5 92.0 % pgood low-level voltage v pglow i_sink = 2ma 0.35 v pgood leakage current i pglkg pgood = 5v 20 150 na pgood timing v out rising threshold to pgood rising (note 11) t pgr 1.1 5 ms v out falling threshold to pgood falling t pgf 75 s reference section internal reference voltage v ref 0.600 v reference voltage accuracy t a = 0c to +85c -0.75 +0.75 % t a = -40c to +125c -1.00 +1.00 % fb bias current i fblkg -40 0 40 na pwm controller error amplifiers input common-mode range v in = 12v 0 v cc - 2 v dc gain v in = 12v 88 db gain-bw product gbw v in = 12v 8 mhz slew rate sr v in = 12v 2.0 v/s comp v ol v in = 12v 0.4 v comp v oh v in = 12v 2.6 v comp sink current (note 12) v comp = 2.5v 30 ma comp source current (note 12) v comp = 2.5v 30 ma pwm regulator minimum off-time t off_min 308 412 ns minimum on-time (note 12) t on_min 40 60 ns peak-to-peak sawtooth amplitude dv ramp v in = 20v 1.0 v v in = 12v 0.6 v ramp offset 1.0 v switching frequency switching frequency f sw rt pin connect to sgnd 250 300 350 khz switching frequency rt pin connect to vcc or float 515 600 645 khz switching frequency r t = 36k 890 1050 1195 khz switching frequency r t = 16.5k 1650 2000 2375 khz r t voltage v rt r t = 36k 770 mv synchronization sync synchronization range (note 12) f sync r t = 0 354 1000 khz diode emulation mode detection mod/sync threshold high (note 12) v modethh 1.1 1.6 2.1 v mod/sync hysteresis (note 12) v modehyst 200 mv diode emulation phase threshold (note 10) v cross v in = 12v -3 mv overvoltage protection unless otherwise noted, typical specifications are measured at v in = 7v to 42v, v out = 1.2v, c_v cc = 10f, t a = +25c. boldface limits apply across the internal junction temperature range, -40c to +125c . (continued) parameter symbol test conditions min (note 9) typ max (note 9) unit
isl8215m 2. specifications fn8878 rev.1.00 page 13 of 41 aug 30, 2017 ovp threshold v ovth 116 121 127 % overcurrent protection ocp threshold (note 14) i octh r ocset resistor open, at +125c junction 19.4 a over-temperature over-temperature shutdown (controller junction temperature) t ot-th 150 c over-temperature hysteresis t ot-hys 15 c notes: 7. in normal operation, where the device is supplied with voltag e on the vin pin, the vcc pin provides a 5v output capable of sourcing 75ma (minimum). this is the total shutdown current wit h v in = 7v and 42v. 8. operating current is the supply current consumed when the dev ice is active but not switching. it does not include gate drive current. 9. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established b y characterization and are not production tested. controller is i ndependently tested prior to module assembly. 10. threshold voltage at phase pin for turning off the bottom mo sfet during dem. 11. when soft-start time is less than 4.5ms, t pgr increases. with internal soft-start (the fastest soft-start tim e), t pgr increases close to its maximum limit 5ms. 12. compliance to limits is assur ed by characterization and desi gn. 13. maximum limit 100% production tested up to 5v. 14. v in = 24v, v out = 3.3v at 125c junction. unless otherwise noted, typical specifications are measured at v in = 7v to 42v, v out = 1.2v, c_v cc = 10f, t a = +25c. boldface limits apply across the internal junction temperature range, -40c to +125c . (continued) parameter symbol test conditions min (note 9) typ max (note 9) unit
isl8215m 3. typical performance curves fn8878 rev.1.00 page 14 of 41 aug 30, 2017 3. typical performance curves 3.1 efficiency performance operating condition: t a = +25c, no air flow. device in p wm mode. typical values are us ed unless otherwise noted. figure 8. v in = 7v figure 9. v in = 12v figure 10. v in = 24v figure 11. v in = 30v figure 12. v in = 36v figure 13. v in = 42v 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.9vout, 300khz 1vout, 300khz 1.2vout, 300khz 1.5vout, 300khz 1.8vout, 300khz 2.5vout, 300khz 3.3vout, 300khz 5vout, 300khz efficiency (%) load current (a) 60 65 70 75 80 85 90 95 100 0123456789101112131415 0.9vout, 300khz 1vout, 300khz 1.2vout, 300khz 1.5vout, 300khz 1.8vout, 300khz 2.5vout, 300khz 3.3vout, 300khz 5vout, 300khz efficiency (%) load current (a) 55 60 65 70 75 80 85 90 95 100 0123456789101112131415 0.9vout, 300khz 1vout, 300khz 1.2vout, 300khz 1.5vout, 300khz 1.8vout, 300khz 2.5vout, 300khz 3.3vout, 300khz 5vout, 300khz 12vout, 600khz efficiency (%) load current (a) 55 60 65 70 75 80 85 90 95 100 0123456789101112131415 0.9vout, 300khz 1vout, 300khz 1.2vout, 300khz 1.5vout, 300khz 1.8vout, 300khz 2.5vout, 300khz 3.3vout, 300khz 5vout, 300khz 12vout, 600khz efficiency (%) load current (a) 50 55 60 65 70 75 80 85 90 95 100 0123456789101112131415 0.9vout, 300khz 1vout, 300khz 1.2vout, 300khz 1.5vout, 300khz 1.8vout, 300khz 2.5vout, 300khz 3.3vout, 300khz 5vout, 300khz 12vout, 600khz efficiency (%) load current (a) 50 55 60 65 70 75 80 85 90 95 100 0123456789101112131415 0.9vout, 300khz 1vout, 300khz 1.2vout, 300khz 1.5vout, 300khz 1.8vout, 300khz 2.5vout, 300khz 3.3vout, 300khz 5vout, 300khz 12vout, 600khz efficiency (%) load current (a)
isl8215m 3. typical performance curves fn8878 rev.1.00 page 15 of 41 aug 30, 2017 3.2 output voltage ripple operating condition: t a = +25c, no air flow. v in = 24v, ccm mode. typical values are used unless otherwise note d. figure 14. output ripple, v out = 1.2v, f sw = 300khz, c out = 4x100 f ceramic + 1x470 f poscap figure 15. output ripple, v out = 1.8v, f sw = 300khz, c out = 4x100 f ceramic + 1x470 f poscap figure 16. output ripple, v out = 2.5v, f sw = 300khz, c out = 4x100 f ceramic + 1x470 f poscap figure 17. output ripple, v out = 3.3v, f sw = 300khz, c out = 4x100 f ceramic + 1x470 f poscap figure 18. output ripple, v out = 5v, f sw = 300khz, c out = 4x100 f ceramic + 1x330 f poscap figure 19. output ripple, v out = 12v, f sw = 600khz, c out = 12x22 f ceramic + 2x150 f poscap 2s/div v out 20mv/div v out 20mv/div i out = 0a i out = 15a 2s/div v out 20mv/div v out 20mv/div i out = 0a i out = 15a 2s/div v out 20mv/div v out 20mv/div i out = 0a i out = 15a 2s/div i out 15a v out 20mv/div v out 20mv/div i out = 0a 1s/div i out 15a v out 20mv/div i out = 0a v out 20mv/div 1s/div v out 20mv/div v out 20mv/div i out = 0a i out 15a
isl8215m 3. typical performance curves fn8878 rev.1.00 page 16 of 41 aug 30, 2017 3.3 load transient response performance operating condition: t a = +25c, no air flow. v in = 24v, ccm mode, 0a - 7.5a, 2.5a/s step load. typical values are used unless otherwise noted. figure 20. v out = 1.2v, f sw = 300khz, c out =4x100 f ceramic + 1x470 f poscap figure 21. v out = 1.8v, f sw = 300khz, c out = 4x100 f ceramic + 1x470 f poscap figure 22. v out =2.5v, f sw = 300khz, c out = 4x100 f ceramic + 1x470 f poscap figure 23. v out = 3.3v, f sw = 300khz, c out =4x100 f ceramic + 1x470 f poscap figure 24. v out =5v, f sw = 300khz, c out =4x100 f ceramic + 1x330 f poscap figure 25. v out = 12v, f sw = 600khz, c out =12x22 f ceramic + 2x150 f poscap 500s/div i out 5a/div v out 100mv/div 500s/div i out 5a/div v out 100mv/div 500s/div i out 5a/div v out 100mv/div 500s/div i out 5a/div v out 100mv/div 500s/div i out 5a/div v out 100mv/div i out 5a/div v out 100mv/div 500s/div
isl8215m 3. typical performance curves fn8878 rev.1.00 page 17 of 41 aug 30, 2017 3.4 start-up waveforms 3.5 derating operating condition: t a = +25c, no air flow. v in = 24v, f sw = 300khz, c out = 4x100f ceramic + 1x330f poscap, ccm mode. typical values are used unless otherwise noted. figure 26. start-up waveforms; v out = 5v, i out = 0a, figure 27. start-up waveforms; v out = 5v, i out = 15a figure 28. shutdown waveforms; v out = 5v, i out = 0.5a figure 29. shutdown waveforms; v out = 5v, i out =15a figure 30. ocp response; output short-circuited from no load to ground and released, v out = 5v, i out = 0a figure 31. ocp response; output short-circuited from 15a to ground and released, v out = 5v, i out =15a 5ms/div v out 2.50v/div pgood 2v/div en 1v/div pgood 2v/div v out 2.50v/div en 1v/div 5ms/div 5ms/div v out 2.50v/div en 1v/div pgood 2v/div en 1v/div v out 2.50v/div pgood 2v/div 5ms/div 50ms/div i out = 20a/div pgood 2v/div v out = 4v/div 50ms/div v out = 4v/div pgood 2v/div i out = 20a/div
isl8215m 3. typical performance curves fn8878 rev.1.00 page 18 of 41 aug 30, 2017 operating condition: v in = 24v . all of the following curves were plotted at t j = +120c. figure 32. pwm/ccm mode, v out = 1.2v, f sw = 300khz figure 33. pwm/ccm mode, v out = 1.8v, f sw = 300khz figure 34. pwm/ccm mode, v out = 2.5v, f sw = 300khz figure 35. pwm/ccm mode, v out = 3.3v, f sw = 300khz figure 36. pwm/ccm mode, v out = 5v, f sw = 300khz figure 37. pwm/ccm mode, v out = 12v, f sw = 600khz load current (a) 0 2 4 6 8 10 12 14 16 25 35 45 55 65 75 85 95 105 115 125 ambient temperature (c) 0lfm 200lfm 400lfm 0 2 4 6 8 10 12 14 16 25 35 45 55 65 75 85 95 105 115 125 ambient temperature (c) 0lfm 200lfm 400lfm load current (a) 0 2 4 6 8 10 12 14 16 25 35 45 55 65 75 85 95 105 115 125 ambient temperature (c) 0lfm 200lfm 400lfm load current (a) load current (a) 0 2 4 6 8 10 12 14 16 25 35 45 55 65 75 85 95 105 115 125 ambient temperature (c) 0lfm 200lfm 400lfm load current (a) 0 2 4 6 8 10 12 14 16 25 35 45 55 65 75 85 95 105 115 125 ambient temperature (c) 0flm 200lfm 400lfm 0 2 4 6 8 10 12 14 16 25 35 45 55 65 75 85 95 105 115 125 ambient temperature (c) 0lfm 200lfm 400lfm load current (a)
isl8215m 4. functional description fn8878 rev.1.00 page 19 of 41 aug 30, 2017 4. functional description 4.1 power-good indicator the power-good signal can be used to monitor the status of the output voltage for undervoltage and overvoltage conditions. this open-drain, pgood output is asserted whenever the output v oltage is within 12.5% of the selected target value. this voltage is measured through the feedback resistiv e divider henc e referenced to the internal 0.6v reference. the pgood assertion occurs aft er a 1.1ms blanking delay upon the output v oltage reaching the regula tion window. pgood is deasserted without any delay when an output undervoltage or ove rvoltage is detected or when en is pulled low. 4.2 self-enable operation an internal pull-up resistor from en to vcc allows for self-ena bling operation. leaving the en pin floating enables the isl8215m as soon as vin reaches t he uvlo threshold, at which po int the soft-start circuitry is activated. for operations in which the isl 8215m is required to turn on at a specific input voltage level, external circuitry must be implemented to control the voltage applied on the en pin throug h a resistor divider. an optional zener (d1 as shown in figure 39 ) may also be required to maintain the en voltage within the re commended operating conditions. 4.3 enable driving the en pin high or low respectively enables or disables operations of the isl8215m. when the en pin voltage reaches 1.6v, an initialization of the isl 8215m internal circuit is per formed. pulling the en low disabl es all internal circuitry to achieve a low standby current and discharges the ss/trk pin to gnd by an internal mosfet with 70 r ds(on) . 4.4 prebiased power-up the isl8215m has the ability to soft-start with a prebiased out put. the output voltage will not be pulled down during prebiased startup. pwm operations will initiate only when the s oft-start ramp reaches the pre biased voltage times the resistive divider ratio. overvolta ge protection is active durin g soft-start operations. figure 38. self-enable operation figure 39. 18v in minimum self-enable operation #! $ ! " $ !

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isl8215m 4. functional description fn8878 rev.1.00 page 20 of 41 aug 30, 2017 4.5 pwm/ccm mode tying the mod/sync pin to signa l ground or leaving it floating selects the pwm only mode of operation. in this mode, the isl8215m operates at a constant frequency at all load curre nts. while this mode provides lower conversion efficiency at light current load, it may be som etimes required for applicatio ns sensitive to electromagnetic interferences. 4.6 psm/dem light-load efficiency mode tying the mod/sync pin to vcc se lects the psm/de m enhanced ligh t-load efficiency mode of operation. in this mode, the isl8215m operates in high-ef ficiency diode emulation mode ( dem) and pulse skipping mode (psm) at light-load conditions. the inductor current is not allowed to reverse (dis continuous operation) while at very light loads, and the isl8215m enters the pulse skipping function. although this mode provides increased conversion efficiency at light load, it also increases the output ripple voltage and operates at a non- constant frequency. 4.7 internal 5v linear regulator (v cc ) an internal low dropout regulator powers all isl8215m internal circuitry allowing the device to operate from a single, wide-input voltage rail from 7v to 42v. for proper operation, t he output of this internal ldo, v cc , should be decoupled to power ground with a 10f capacitor positioned as close as possi ble to the pin. no other circ uitry should be connected to vcc. 4.8 gate control logic optimization the isl8215m implements a specifi c proprietary mosfet gates con trol logic that optimizes the performance over a wide range of operating conditions. thi s circuitry provides adaptive dead time control by monitoring the real gate waveforms of both the high-side and low-side mosfets. a shoot-through contro l logic provides a 16ns dead time to ensure that both the upper and lower mosfets will not turn on simultaneously and cau se a shoot-through condition. figure 40. prebiased power-up waveform, prebiased voltage = 3.0v, v out = 3.3v, i out = no load v out 100mv/div v in 12v/div pgood 2v/div 5ms/div
isl8215m 5. application information fn8878 rev.1.00 page 21 of 41 aug 30, 2017 5. application information 5.1 output voltage programming the isl8215m supports an adjustable output voltage range of 0.6 v to 12v. a single resistor, r 2 , placed from fb to sgnd sets the output vol tage according to (eq. 1) . where r 1 = fixed high-side resistor value of 43.2k 1% tolerance insid e the module and r 2 = resistor connected from fb to sgnd in k. table 3 assists in selecting th e value of resistor r 2 for typical output v oltages. for maximum output voltage accura cy, r 2 should be selected with a to lerance of 0.1% or better. 5.2 switching frequency selection the switching frequency of the i sl8215m is programmable from 30 0khz to 2mhz typical and is set by a resistor connected from the rt p in to sgnd according to (eq. 2) : where f sw is the switching frequency in mhz. the switching frequency can be set to 300khz when the rt pin is tied to ground. the switching frequency can be increased to 600khz if the rt pin is tied to vcc or left floating. switch ing frequency selection is a trade-off between efficiency, output voltage ripple, and load transient response requirements . typically, a low switching frequency improves efficiency by reducing mosfet switching lo sses while a high switching freq uency improves the output vo ltage ripple and transient response in conjunction with the value and type of the output c apacitance. the frequency setting curve shown in figure 41 assists in selecting the corr ect value for the resistor r t . table 3. output voltage resistor settings v out (v) r 2 e192 series 0.6 open 0.8 130k 0.85 104k 0.90 86.6k 0.95 74.1k 1.0 64.9k 1.1 51.7k 1.2 43.2k 1.5 28.7k 1.8 21.5k 2.5 13.7k 3.3 9.53k 5 5.90k 12 2.26k r 2 r 1 0.6 ? ?? v out 0.6 C ?? ---------------------------------- - = (eq. 1) r t 39.2 f sw ----------- 1.96 C ?? ?? k ? = (eq. 2)
isl8215m 5. application information fn8878 rev.1.00 page 22 of 41 aug 30, 2017 when using the isl8215m internal oscillator to control switchin g operations, the desired control scheme must be configured. in this mode, the mod /sync pin selects the required configuration. 5.3 external frequency synchronization the isl8215m can be synchronized t o an external clock applied o n the mod/sync pin. the ex ternal clock should be a square pulse waveform with a frequency in the range of 354khz - 1mhz. the programmed fr equency of the isl8215m module, which is set by the resis tor connected to the rt pin sh ould be lower than the external clock frequency. the duty cycle of the external clock shou ld be within 30% to 70% (typica lly 50%), while the amplitude should be in the range of 3v to 5v. to ensure proper operation, the e xternal clock frequency must b e at least 18% higher than the programmed default frequency of the module. the modul e should be disabled before t urning off the external clock. when frequency synchronization is in effect, the isl8215m operates in forced p wm mode across all loads. 5.4 soft-start operation the isl8215m provides soft-star t operations for applications wh ere inrush current during startup need be reduced. a soft-start capacitor placed between the ss/trk pin and signal ground adjusts the soft-start output voltage ramp rate. the typical soft-start time is based on the soft-sta rt capacitor va lue and set according to (eq. 3) : where c ss is in nf and t ss in ms. the soft-start time setting curve shown in figure 42 assists in selecting the corr ect value for the capacitor c ss . when the soft-start time set by external c ss or tracking is less than 1.5ms, an internal soft-start circuit ry of 1.5ms will take over the soft-start function. furthermore , overvoltage protection is act ive during soft-starting operation. figure 41. r t vs switching frequency f sw 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 20406080100120140 f sw (khz) rt (k) t ss 0.6v c ss 2 ----------- ?? ?? = (eq. 3)
isl8215m 5. application information fn8878 rev.1.00 page 23 of 41 aug 30, 2017 5.5 tracking operation the isl8215m can be configured to track an external supply, eit her coincidently or ratiometrically. to implement this functionality, a tracking resist or divider is connected between the external supply output (master rail) and ground. the center point of this resistor div ider is connected to the ss/tr k pin of isl8215m. coincident tracking is achieved when both the ma ster rail and i sl8215m output rail reach the ir respective regulation voltage levels with the same slope. as shown in figure 44 , the master rail and the isl82 15m output rail reach regulation at two different times. coinciden t tracking can be achieved by set ting the external resistor di vider ratio (rtrk_t/rtrk_b) equal to the feedback resistor divider ratio (r 1 /r 2 ) of the isl8215m. table 3 on page 21 can assist in selecting the appropriate resistor value fo r different output voltages. figure 42. c ss vs t ss figure 43. isl8215m v out = 1.2v - coincidental tracking of master rail - divider ratio of 1:1 figure 44. coincidental tracking of master rail 0 10 20 30 40 50 60 70 80 90 100 110 0 5 10 15 20 25 30 35 soft-start ramp rate - t ss (ms) c ss (nf) ! !
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isl8215m 5. application information fn8878 rev.1.00 page 24 of 41 aug 30, 2017 ratiometric tracking is achieved when the master rail and the i sl8215m output r ail both reach their fin al regulation value at the same time but with diff erent slopes, as shown in figure 45 . use (eq. 4) to calculate the resistor divider ratio (rtrk_t/rtrk_b) to implement ratiometric tracking. note that r1 is a fixed high-si de resistor of value 43.2k. when the voltage at the ss/trk pin reaches ~550mv, the output v oltage is decided by the internal reference of the isl8215m controller. in addition, the tracking resistor divider of the master rail should include resistors of values less tha n 10k to minimize the im pact of the 2a soft-start current on th e tracking function. 5.6 input voltage range the isl8215m is designed to oper ate from a single wide input su pply ranging from 7v dc to 42v dc. limitations on the minimum on-time and minimum off-time required by the isl8215m l imit the minimum and maximum conversion ratios, or duty cycles, supported. by extension, the supported input volta ge range for a selected output voltage and selected operating frequency may be effectively reduced. the maximum input voltage is limited by the minimum on-time (t on(min) )as shown in (eq. 5) . where t on(min) = 60ns worst case and f sw is the switching frequency in hz. the minimum input voltage is li mited by the minimum off-time (t off(min) ), on-resistance of the high-side fet, r ds(on) , series resistance of the inductor (r l ), and the load current (i out ) as shown in (eq. 6) . because of the temperature coefficient of the mosfet and in ductor, note that the minimum v alue of v in will occur at the +125c at r l = 9.7m and r ds(on) = 18.75m. where t off(min) = 412ns worst case. 5.7 input capacitor selection the important parameters for t he input capacitor(s) are the vol tage rating and the rms cu rrent rating. for reliable operation, select input capacitors with voltage and current rat ings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating s hould be at least 1.25 times gr eater than the maximum input voltage and 1.5 times is a cons ervative guideline. the ac rms input current varies with the load given in (eq. 7) : where d is duty cy cle of the pwm. figure 45. ratiometric tracking of master rail v master rail rtrk_b rtrk_b rtrk_t + ---------------------------------------------------- - ? 0.6 = (eq. 4) time output voltage isl8215m v out master rail v in max ?? v out t on min ?? f sw ? ---------------------------------------- - ?? ?? ?? ? (eq. 5) v in min ?? v out i out r ds(on) r l + ?? ? + 1t C off min ?? f sw ? --------------------------------------------------------------- ------------------ - ?? ?? ?? ? (eq. 6) i rms d1 d C ?? i out ? = (eq. 7)
isl8215m 5. application information fn8878 rev.1.00 page 25 of 41 aug 30, 2017 the maximum rms current supplie d by the input capacitance occur s at v in = 2 x v out , d = 50% as shown in (eq. 8) : refer to the capacitor vendor to check the rms current rating. it should be noted that the current rating is decided by the ambient temperature or temperature rise. e ach 1210 size 10f lo w esr capacitor is typically good for 2a to 3a rms ripple current. use a mix of input bypass capacitors to control the voltage str ess across the mosfets. use cer amic capacitors for the high frequency decoupling and bulk capacitors to supply the rms curr ent. small ceramic capacitors can be placed very close to the mosfets to suppress the volta ge induced in the parasitic ci rcuit impedances. solid tantalum capacitors can be used, however, caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge current at power-up. 5.8 output capacitor selection the isl8215m is designed for low output voltage ripple. in gene ral, output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and lo ad transients, which can be me t with bulk output capacitors that have adequately low esr and esl. high frequency capacito rs initially supply the transient curren t and slow the slew rate of lo ad transient seen by the bulk capacitors. the bulk f ilter capacitor value s are generally dete rmined by the esr and esl and voltage rating requirements, as well as actual capacitance requirements. high frequency decoupling capacito rs should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low esr/esl components. consult with the manufacturer o f the load circuitry for specifi c decoupling requirements. use only specialized low esr cap acitors intended for switching regulator applications for th e bulk capacito rs. in most cases, multiple small case electro lytic capacitors perform bett er than a single large case capacitor. in conclusion, the output capacitors must meet the following cr iteria: (1) they must have suff icient bulk capacitan ce to sustain the ou tput voltage during a load transient while the output inductor current is slewing to the value of the load transient. (2) the esr must be sufficiently l ow to meet the desired output voltage ripple due to the output inductor current. the recommended output capacitor value for the isl8215m is betw een 400f to 1000f. see tables 1 and 2 on page 9 for more capacitor information. all ceramic capacitors are possible with loop analysis to ensure stability. (eq. 8) i rms 1 2 -- - i out ? =
isl8215m 6. protection circuits fn8878 rev.1.00 page 26 of 41 aug 30, 2017 6. protection circuits 6.1 undervoltage lockout the isl8215m includes uvlo protection, which keeps the device i n a reset condition until a pr oper operating voltage is applied. it also shuts down the isl8215m if the operating volta ge drops below a predefined value. upon assertion of the uvlo state, the controller is co mpletely disabled. pgood is val id and will be deasserted. 6.2 overcurrent protection the isl8215m uses the lower mosfet's on-resistance, r ds(on) , to monitor the current in the converter. the sensed voltage drop across the mosfets drain-to-source is compared to a threshold voltage s et by the resistor, r ocset , connected from the ocs pin to ground. because r ds(on) is higher at hot temperatures a nd lower at cold temperatures, the ocp setpoint at room and cold temperatures will be higher than the ocp setpoint at hot temperatures. for applications involving less than 15a load, it is recommende d to further reduce the ocp se tpoint to improve the system reliability, and (eq. 9) can be used to calculate the v alue of the ocp set resistor. where, i o = desired full load current (a). r ocset = resistor connected t o the ocs pin (k). r nom = r ocset resistor to ensure 15a full load operation (k). r ocset values for ensuring 15a full load operation: ? 20m for 3.3v output and below (simulating a d o not populate (dnp) condition). ? 205k for 5v output ? 118k for 12v output in (eq. 9) the typical load current to hit ocp at +120c is set to around 20% higher than the desir ed full load current. the 20% margin is due to the controller ocp and the mosfet r ds(on) tolerance. if an overcurrent is detected, th e upper mosfet remains off and the lower mosfet remains on until the next cycle. as a result, the converter skips a pulse. when the overload conditio n is removed, the converter res umes normal operation. if an overcurrent is detected for two consecutive clock cycles, the m odule enters hiccup mode by turn ing off the gate driver and entering soft-start. the isl8215m stays off for 50ms before try ing to restart and continues to cycle through soft-start until the overcurrent condition is rem oved. hiccup mode is active dur ing soft-start, so ensure that the peak inductor current does not exceed the overcurrent threshold during soft-start. when ocp is triggered, the ss/trk pin is pulled to ground by an internal mosfet for hiccup restart. when configured to track another voltage rail, the s s/trk pin rises up much faster than the internal minimum soft-start ramp. the voltage reference is then clamped to the internal minimum soft-start ra mp. thus, smooth soft-start hiccup is achieved even with the tracking function. r ocset 26.1 r nom i o 15 ? ?? ?? ?? r nom 1i o 15 ? ?? C ?? 26.1 + ? ?? --------------------------------------------------------------- ---------------- k ? = (eq. 9)
isl8215m 6. protection circuits fn8878 rev.1.00 page 27 of 41 aug 30, 2017 6.3 overvoltage protection the overvoltage set point is set at 121% of the nominal output voltage set by the feedback resistors. in case of an overvoltage event, the module w ill attempt to bring the output voltage back into regulation by keeping the upper mosfet turned off and the lower mosfet turned on. if the overvoltage c ondition has been corrected and the output voltage returns to 110% of the nominal output vol tage, both high-side and low-s ide mosfets will be turned off until the output voltage drops to the nominal voltage to start work in normal pwm switch ing. 6.4 over-temperature protection the ic incorporates a n over-temperature pr otection circuit that shuts down the ic when a di e temperature of +150c is reached. normal operati on resumes when the die temperature drop s below +145c through the initiation of a full soft- start cycle. during otp shutdown, the ic consumes only 100a cu rrent. when the controller is disabled, thermal protection is inactive. this he lps achieve a very low shutdown current of 5a.
isl8215m 7. layout guidelines fn8878 rev.1.00 page 28 of 41 aug 30, 2017 7. layout guidelines careful attention to layout requ irements is nece ssary for succe ssful implementation of an isl8215m based dc/dc converter. the isl8215m switches at a very high frequency and, therefore, the switching tim es are very short. at these switching frequencies, even the shortest trace has significant impedance. also, the peak gate dr ive current rises significantl y in an extremely short time. trans ition speed of th e current fro m one device to another cause s voltage spikes across the interconnecting impedances and pa rasitic circuit elements. thes e voltage spikes can degrade efficiency, generate emi, and increase device overvoltage stre ss and ringing. careful compone nt selection and pr oper pc board layout minimize the magnitude of these voltage spikes. 7.1 layout considerations (1) place the input cap acitors and high frequency decoupling cer amic capacitors between vin and pgnd, as close to the module as possible. the loop formed by the input capacitor, vin pad, and pgnd must be as small as possible to minimize the high fre quency noise. the out put capacitors should be placed close to the loa d. use short, wide copper planes to connect the output capac itors to the load for avoidin g any parasitic inductan ces and resistances. an illustrative layout example is shown in figures 46 and 47 . (2) vin, vout, and pgnd should use large copper planes to minimi ze conduction loss and thermal stress. use enough vias to connect the power planes in different layers. (3) use full ground planes in the internal layers (underneath th e module) with shared sgnd and pgnd to simplify the layout design. it is recommende d to use slots, as shown in figure 48 on page 29 to ensure that the switching current avoids the sgnd pad of the module. it is recommended to use as much gnd plane as possible for the layer directly above the bottom layer (containing components like input caps, output caps, etc). use the top and bottom layer to route en, vcc, and pgood signals. (4) for a switching frequency of 300khz and a 42v input, connect a 4.02 1206 resistor and a 270pf 100v x7r 0603 capacitor in series from ph to vin . de-rate the re sistor size f or switching frequencies higher than 300khz. calculate the power dissipated in resistor r5 (p cal ) by using the formula c ? v 2 ? f, where, ? c = 270pf ? v = input voltage ? f = frequency of operation. for derating purposes, the nomin al power handling capability of the resistor package si ze should be a t least p cal /0.65. the 65% derating is derived by looking at the resistor operatio n at +100c ambient temperat ure. use a standard thick film chip resistor dat asheet to find the co rrect resistor packa ge size for different switching frequencies and input voltage. (5) make sure that ug1 and ug2 (d6 and k4) are connected externa lly through a pcb trace. a s imilar connection should be made for the two en pins (a6 and a8). (refer to the pin conf iguration on page 7 and the pin description table on page 8 .) (6) use a remote sensing trace to connect to the vout+ of load f or achieving a tight output voltage regulation. route the remote sense trace underneath the gnd layer and avoid routing t he sense lines near noisy planes such as phase node. place a 2 resistor close to rs pin for d amping the noise on the traces. (7) to avoid ground bounc ing issues, place the v in return and the v out return diagonally opposite to each other. this will also ensure that the switching noi se generated by the power-tra in will have a minimal effect on the controller operation. (8) do not unnecessarily oversize the copper islands for the pha se node. because the phase nod es are subjected to very high dv/dt voltages, the paras itic capacitor form ed between the se islands and the surrounding circuitry will tend to couple the switching noise. cauti on must be taken to ensure tha t none of the sensi tive signal traces are routed close to the phase node plane. (9) place the vcc bypass capacitor underneath the vcc pin, and c onnect its ground to pgnd pa d. connect the low side feedback resistor and the deco upling cap for vout1 to sgnd pad.
isl8215m 7. layout guidelines fn8878 rev.1.00 page 29 of 41 aug 30, 2017 figure 46. layout example - top layer figure 47. layout example - bottom layer figure 48. layout example - sgnd i s connected to pgnd through int ernal layer pgnd phase node cout cout vout sgnd cin cin vin pgnd pgnd phase node cout cout vout cin cin vin pgnd inner layer inner layer inner layer isl8215m sgnd pad isl8215m pgnd pad slots in pcb
isl8215m 8. thermal considerations fn8878 rev.1.00 page 30 of 41 aug 30, 2017 8. thermal considerations experimental power loss curves, along with ? ja from thermal modeling analysis, can be used to evaluate the th ermal consideration for the module. the derating curves are derived f rom the maximum power allowed while maintaining temperature below the maximum ju nction temperature of +120c. i n applications in which the sy stem parameters and layout are different from the evaluation board, the customer can adjus t the margin of safety. all dera ting curves are obtained from t he tests on a 4-layer thermal test board 4.5x3 inches in size. ref er to tb379 for more details. in the act ual applicati on, other heat sources and design margins should be considered.
isl8215m 9. package description fn8878 rev.1.00 page 31 of 41 aug 30, 2017 9. package description the structure of the isl8215m belongs to the high density array no-lead package (hda). this kind of package has advantages, such as good thermal and electrical conductivity, l ow weight, and small size. the h da package is applicable for surface mounting technology and i s being more readily used in t he industry. the isl8215m contai ns several types of devices, including resistors, capacitors, inductors, and control ics. th e isl8215m is a copp er leadframe based package with exposed copper thermal pads, which have good electrical and thermal con ductivity. the copper lead frame and multi-component assembly is overmolded with polymer mold compound to protect th ese devices. the package outline, typical pcb layout pattern design, and typ ical stencil pattern des ign are shown in the package outline drawing starting on page 34 . the module has a small size of 19mmx13mmx5.3mm. 9.1 pcb layout pattern design the bottom of the isl8215m is a lead-frame footprint, which is attached to the pcb by a su rface mounting process. the pcb layout pattern is shown on page 37 and page 38 . the pcb layout pattern is an array of solder mask defined pcb lands that align with the perimeters of the hda exposed pads and i/o termination dimensions. the thermal lands on the pcb layout also feature an array of solder mask defined lands and s hould match 1:1 with the package exposed die pad perimeters. the exposed solder m ask defined pcb land area shoul d be 50-80% of the avai lable module i/o area. 9.2 thermal vias a grid of 1.0mm to 1.2mm pitch th ermal vias, which drops down a nd connects to buried copper plane(s), should be placed under the thermal land. the vias should be about 0.3mm to 0.33m m in diameter with the barrel plated to about 1.0 ounce copper. although adding more vi as (by decreasing via pitch) wil l improve the thermal performance, diminishing returns will be seen as more and more vias are added. simply use as man y vias as practical for the thermal land size and your board design rules allow. 9.3 stencil pattern design reflowed solder joints on the pe rimeter i/o lands should have a bout a 50m to 75m (2 mil to 3 mil) standoff height. the solder paste stencil design is t he first step in developing opt imized, reliable solder joints. stencil ape rture size to solder mask defined pcb land size ratio should typically be 1:1. the apertu re width can be reduced slightly to help prevent solder bridgin g between adjacent i/o l ands. a typical solder stencil pattern is shown on page 35 and page 36 . the user should consider the symmetry of the whole stencil pa ttern when designing its pads. a laser cut, stainless steel st encil with electropolished trapezoidal walls is recommended. electropolishing smooths th e aperture walls resulting i n reduced surface friction and better paste release, which reduces voids. using a trapezoidal section aperture (tsa) also prom otes paste release and forms a brick like paste deposit that assists in firm component place ment. a 0.1mm to 0.15mm stencil thickness is recommended for this large pitch (1.3mm) hda.
isl8215m 9. package description fn8878 rev.1.00 page 32 of 41 aug 30, 2017 9.4 reflow parameters due to the low mount height of the hda, no clean type 3 solde r paste per ansi/j-std-005 is recommended. nitrogen purge is also recommended during reflow. a system board reflow profile depends on the thermal mass of the entire populated board, so it is not pr actical to define a specific so ldering profile just for the hda. the profile given in figure 49 is provided as a guideline, to be customized for varying manufa cturing practices and applications. figure 49. typical reflow profile 0 300 100 150 200 250 350 0 50 100 150 200 250 300 temperature (c) duration (s) ramp rate 1.5c from +70c to +90c peak temperature ~+245c; typically 60s-150s above +217c keep less than 30s within 5c of peak temp. slow ramp (3c/s max) and soak from +150c to +200c for 60s~180s
isl8215m 10. revision history fn8878 rev.1.00 page 33 of 41 aug 30, 2017 10. revision history rev. date description 1.00 aug 30, 2017 updated figure 2 on page 1. updated table in section 1.5, pin descriptions. added r5 (package) column to table 1 on page 9. updated over-temperature shutdown value on page 13. updated requirements in section 7.1, layout considerations. 0.00 aug 1, 2017 initial release
fn8878 rev.1.00 page 34 of 41 aug 30, 2017 isl8215m 11. package outline drawing 11. package outline drawing y22.19x13 22 i/o 19mmx13mmx5.30mm hda module rev 1, 11/16 bottom view side view top view represents the basic land grid pitch. these 17 i/os are centered in a fixed row 3. 2. all dimensions are in millimeters. 1. notes: dimensioning and tolerancing per asme y14.5-2009. tolerance for exposed pad edge l ocation dimension is 0.1mm. 4. 5. c seating detail a terminal #a1 index area 19.00 13.00 0.10 c 2x 2x a b see detail a 18 0.10 0.10 0.05 c 12.00 datum a 18.00 datum b pin 1 indicator co.30 ref. 1716151413121110987654321 a b c d e f g h j k l m m m m 5.30 max 0.025 (scale 2:1) 1.00 3 17x0.60 0.05 0.10 c a b 0.05 c m m 0.50 ref. 0.50 ref. 17x0.60 0.05 r0.100 ref. 1.00 and column matrix at 1.0mm pitch bsc. cab 0.10 mcab c a b 0.10 c plane 0.10 c 0.08 c 2 3 2 for the most recent package outline drawing, see y22.19x13 .
fn8878 rev.1.00 page 35 of 41 aug 30, 2017 isl8215m 11. package outline drawing recommended solder stencil top view 1 9.500 8.985 8.415 7.985 7.415 6.985 6.415 5.985 5.415 4.985 4.415 0.350 0.000 0.950 1.250 2.550 2.850 4.150 4.450 5.750 6.050 7.350 7.650 8.950 9.500 6.500 5.985 5.415 3.985 3.415 2.985 2.415 1.985 1.415 0.000 4.150 4.900 5.200 5.950 6.500 9.500 7.950 7.650 6.650 6.350 5.350 5.050 4.050 3.750 2.750 2.450 1.450 0.000 0.650 1.550 1.850 2.750 3.050 3.950 4.250 5.150 5.450 6.350 6.650 7.550 9.500 4.900 4.625 3.575 3.300 2.250 0.350 0.000 0.450 0.750 1.550 1.850 2.650 2.950 3.750 4.050 4.850 5.150 5.950 6.500 5.950 recommended solder stencil view 1
fn8878 rev.1.00 page 36 of 41 aug 30, 2017 isl8215m 11. package outline drawing recommended solder stencil top view 2 9.500 8.950 6.950 6.679 6.150 5.850 5.050 3.985 3.415 2.985 2.415 1.985 1.415 0.000 5.985 5.415 4.985 4.415 3.985 3.415 2.985 2.415 0.350 0.000 0.650 0.950 1.950 2.250 3.250 6.500 6.500 4.950 4.679 4.150 3.850 3.050 0.750 0.000 0.300 0.600 0.925 1.650 3.015 3.585 6.500 9.500 8.950 7.850 7.550 6.450 5.985 5.415 4.250 3.325 3.025 2.100 1.800 0.875 0.575 0.000 0.350 9.500 9.000 recommended solder stencil view 2
fn8878 rev.1.00 page 37 of 41 aug 30, 2017 isl8215m 11. package outline drawing recommended positive solder mas k defined pcb land pattern top view 1 6.500 6.000 5.400 4.000 3.400 3.000 2.400 2.000 1.400 0.000 4.100 4.950 5.150 6.000 6.500 6.500 6.000 4.850 4.675 3.525 3.350 2.200 0.400 0.000 0.500 0.700 1.600 1.800 2.700 2.900 3.800 4.000 4.900 5.100 6.000 6.500 9.500 9.000 8.400 8.000 7.400 7.000 6.400 6.000 5.400 5.000 4.400 4.000 3.400 2.000 1.400 0.400 0.000 1.000 1.200 2.600 2.800 4.200 4.400 5.800 6.000 7.400 7.600 9.000 9.500 9.500 9.000 7.900 7.700 6.600 6.400 5.300 5.100 4.000 3.800 2.700 2.500 1.400 0.000 0.600 1.600 1.800 2.800 3.000 4.000 4.200 5.200 5.400 6.400 6.600 7.600 9.500 pcb land pattern view 1
fn8878 rev.1.00 page 38 of 41 aug 30, 2017 isl8215m 11. package outline drawing recommended positive solder m ask defined pcb land pattern top view 2 6.500 4.700 4.100 3.900 3.000 2.400 0.800 0.000 0.350 0.550 0.975 1.700 3.000 3.600 5.000 6.500 6.500 6.000 5.400 5.000 4.400 0.400 0.000 0.700 0.900 2.000 2.200 3.300 6.500 9.500 7.000 6.700 6.100 5.900 0.000 5.000 3.000 2.400 2.000 1.400 9.500 9.500 9.000 7.800 7.600 6.400 6.200 6.000 5.400 5.000 4.300 3.275 3.075 2.050 1.850 0.825 0.625 0.000 0.400 9.500 pcb land pattern view 2
fn8878 rev.1.00 page 39 of 41 aug 30, 2017 isl8215m 11. package outline drawing size details for the 5 exposed pads 9.40 3.80 2.00 2.00 1.78 4.00 2.50 2.60 3.70 7.60 1.90 11.90 6.40 7.00
fn8878 rev.1.00 page 40 of 41 aug 30, 2017 isl8215m 11. package outline drawing terminal and pad edge details (bottom view) 6, 5 6.000 2.200 0.400 0.000 3.300 6.000 6, 5 6, 5 6.000 5.400 5.000 4.700 ref. 4.000 3.400 3.000 2.400 2.000 1.400 0.800 0.000 0.975 1.700 3.000 3.600 4.100 6.000 6, 5 9, 5 7.600 0.600 0.000 1.400 4.300 5.000 5.400 6.000 6.400 9.000 9, 5 9, 5 9.000 0 0.400 1.400 2.000 2.400 3.000 3.400 4.000 4.400 5.000 5.400 6.000 6.400 6.700 ref. 7.000 7.400 8.000 8.400 9.000 9, 5
fn8878 rev.1.00 page 41 of 41 aug 30, 2017 isl8215m 12. about intersil intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form , fit or function of the product. accordi ngly, the reader is cautioned to verify that datasheets are current befo re placing orders. information furnished by intersil is beli eved to be accurate and r eliable. however, no responsibility is assumed by intersil or its subsidiaries for it s use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent righ ts of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2017. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. 12. about intersil intersil corporation is a leadi ng provider of innovative power management and precision analog solutions. the company's products address some of the largest markets within t he industrial and infrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentation, an d related parts, see th e respective product information page found at www.intersil.com . for a listing of definitions and a bbreviations of common terms used in our documents, visit: www.intersil.com/glossary . you can report errors or suggesti ons for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support .

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